The logic circuits of the prior art are generally realised based on field-effect transistors, for example using CMOS (Complementary Metal-Oxide Semiconductor) technology, which associates two types of complementary MOS transistors, one of the n type, the other of the p type, on a same support.
FIG. 1 is a circuit diagram of an example of an inverting logic cell 100, i.e. performing the NO base function, using CMOS technology. The cell 100 comprises an association in series of an N-channel MOS transistor T1 and a P-channel MOS transistor T2 between a node GND for applying a reference potential of the circuit (for example, ground) and a node for applying a DC supply voltage VDD referenced with respect to the node GND. More specifically, the transistor T1 has its source connected to the node GND and its drain connected to the drain of the transistor T2, and the transistor T2 has its source connected to the node a1. The gates of the transistors T1 and T2 are connected to a same node e1 for applying an input logic signal VIN1. The drains of the transistors T1 and T2 are connected to a same node s1 for providing an output logic signal VOUT1. In this example, the input signal VIN1 and the output signal VOUT1 are voltages referenced with respect to the node GND. In FIG. 1, a capacitor CL connected between the output node s1 and the reference node GND has been illustrated, representing the output capacitance of the cell.
The operation of the inverter 100 shown in FIG. 1 is as follows. When the input signal VIN1 is in the high state, for example at a value close to the supply voltage VDD, the transistor T2 is off and the transistor T1 is on. As a result, the signal VOUT1 is maintained in a low state, close to 0 volt. When the input signal VIN1 is a low state, for example at a value close to 0 volt, the transistor T1 is off and the transistor T2 is on. As a result, the signal VOUT1 is maintained in a high state, close to VDD. The cell shown in FIG. 1 thus performs the function of an inverter, i.e. the output logic signal VOUT1 is equal to the complement of the input logic signal VIN.
More generally, all the basic logic functions conventionally used in integrated circuits can be realised by cells having architectures of the same type as the one shown in FIG. 1, i.e. comprising field-effect transistors mounted as resistor voltage divider bridges.
The logic cells of this type, however, have limitations in terms of electrical energy consumption. In particular, it can be shown that a cell of the type described in relation to FIG. 1 dissipates, each time the state of its input signal changes, a quantity of energy E given by the relation:E=0,5*CL*VDD2  [Math 1]
In order to reduce the dynamic consumption of the cells, it is possible to try to reduce their supply voltage VDD. However, in practice, the reduction of the supply voltage is accompanied by a decrease in the threshold voltages of the transistors and consequently by an increase in the leakage currents in the transistors, and thus in the static consumption of the cells.
Another type of logic cells, known as adiabatic, have been proposed in order to reduce the consumption of the cells. In adiabatic logic, rather than abruptly charging and discharging the output capacitances CL of the cells each time their state changes, which is the case in classic logic, an effort is made to effect the charging and discharging of the capacitances CL in a gradual manner. For this purpose, the DC supply voltage VDD used in classic logic is replaced by a periodic variable supply voltage. The adiabatic logic is a dynamic logic, i.e. the output states of the logic cells are only available during a fraction of the period of the clock signal formed by the periodic variable supply voltage. If one designates the duration of charging or discharging the capacitances CL by T, the resistance of the transistor T1 or T2 used to charge or discharge the capacitance CL by RT, and if a periodic supply voltage varying from 0 volt to VDD is considered, it can be shown, as a first approximation (by considering the duration T to be much greater than the time constant RT*CL of the cells), that the quantity of energy E dissipated during a change of state of a cell is expressed by the relation:
                    E        =                  CL          *                      VDD            2                    *                                    2              *              RT              *              CL                        T                                              [                  Math          ⁢                                          ⁢          2                ]            
Thus, if the duration T of charging and discharging the capacitances CL of the cells (corresponding to the time of increase from 0 volt to VDD or of decrease from VDD to 0 volt of the supply voltage) is chosen to be high enough with respect to the time constant RT*CL of the cells, the energy dissipated at each change of state can be reduced in a meaningful manner compared to classic logic circuits of the type described in relation to FIG. 1.
In practice, the adiabatic logic circuits realised using CMOS technology also have limitations in terms of consumption. In particular, in a MOS transistor usually having a non-zero threshold voltage, a residual non-adiabatic energy dissipation inevitably persists at each switching of the transistors of the cell. The reduction of the threshold voltage of the transistors in advanced CMOS technologies makes it possible to reduce this non-adiabatic dynamic dissipation, but is generally accompanied by an increase in the leakage currents, and thus in the static consumption of the cells, which remains significant due to the relatively low frequency of the periodic variable supply voltage.